Digital CCD Line Scan Camera SK 1024 XSD ( Rev.1.0. / 20.09.2005 ) - Manual Page
5
CLT**
CCLK
LVAL***
Data
Video
internally
20 ns
6. Timing Diagram
* The rising edge of ‘SOS’ should not occur within a range of 3 to 25 ns before leading edge of ‘MCLK’.
(Integration Control Timing see below)
** CLT = Camera Line Transfer ( internal line scan camera Signal)
*** The signal ‘LVAL’ contains a ‘CLT’ pulse at the line beginning, which is required for the synchronisation of
the Schäfter+Kirchhoff Interface boards.
If requested, the CCD line scan camera is available without ‘CLT’ pulse at the line beginning of the ‘LVAL’.
Order Code SK 1024 XSD-3
The pixels determining the black level value are the 3th to the 7th before pixel no. 1.
N = Sensor pixels
i = Isolation pixels
o = Overclocking
MCLK
SOS *
Input
Output
ca. 60 ns 35 Clock Cycles N Clock Cycles 4 Clock Cycles min.
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